1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Related Art
In recent years, there is known an FBC (Floating Body Cell) memory device as a semiconductor memory device expected to replace a conventional 1-Transistor 1-Capacitor DRAM. The FBC memory device is configured so that FET's (Field Effect Transistors) are formed each including a floating body (hereinafter, also “body region”) provided on an SOI (Silicon On Insulator) substrate, and so that data “1” or “0” is stored according to the number of majority carriers accumulated in the body region.
If each FBC is an n-channel MISFET, for example, the FBC can store data according to the number of holes accumulated in its body region. If a state in which the number of holes accumulated in the body region is small corresponds to data “0” and a state in which the number of holes accumulated in the body region is large corresponds to data “1”, then a body potential of each memory cell storing therein data “0” (hereinafter, also “0” cell) is relatively low, and that of each memory cell storing therein data “1” (hereinafter, also “1” cell) is relatively high. Due to this, a threshold voltage of the “0” cell is relatively high and a drain current thereof is relatively small. Further, a threshold voltage of the “1” cell is relatively low and a drain current thereof is relatively large. It is possible to discriminate whether a memory cell stores therein data “0” or “1” according to the drain current of the memory cell.
However, FBCs have a fluctuation in drain current. The fluctuation in the drain current among the FBCs mainly results from a fluctuation in threshold voltage among the FBCs. If the fluctuation in the drain current is large, defective (or fail) bit counts of the FBC memory device disadvantageously increase. This phenomenon is described in “Operation Voltage Dependence of Memory Cell Characteristics in Fully Depleted Floating Body Cell”, by T. Shino, et al., IEEE Transaction On Electron Devices, Vol. 52, No. 10, October 2005, pp. 2220-2226. For example, a memory cell the threshold voltage of which is low when the memory cell store therein data “0” and a memory cell the threshold voltage of which is high when the memory cell stores therein data “1” are defective bits.